1. Field
The described technology relates to a semiconductor memory device having a cross point structure and a method for manufacturing the same which comprises a plurality of upper electrodes arranged to extend in one direction, a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes, and a group of memory materials provided between the upper electrodes and the lower electrodes for storage of data.
2. Description of the Related Art
In general, a semiconductor memory device such as DRAM, NOR flash memory, or FeRAM is arranged in which each memory cell comprises a memory element for storage of data and a selecting transistor for selectively operating the memory element. On the other hand, the semiconductor memory having a cross point structure is arranged not including the selecting transistor but having a memory material provided as the memory element at the intersection (cross point) between the bit line and the word line. Since a stored data is read directly from its cross point at the bit line and the word line, the semiconductor memory can be simple in the construction and thus easily increased in the storage size regardless of some drawbacks such as the speed of data reading may be declined by the effect of parasitic current leaked from the unselected cells and the consumption of current may be increased more or less.
It is known that such a cross point memory having the cross point structure has the memory materials implemented by a perovskite material. Examples of the perovskite material are a colossal magneto-resistant (CMR) material and a high-temperature super-conductive (HTSC) material, having an electric resistivity which can be modified by an external control. In particular, the CMR or HTSC material can be varied in the resistivity by short pulses applied to its thin film or bulk body. The pulses to be applied have to be set to a small level in the electric field strength or current density enough to switch the physical state of the material from one to another as well as to give no fracture nor serious damage to the material. The material can thus be modified in the property by the action of the pulses. More specifically, the material can be modified in steps by a series of the pulses. One particular property of the material to be modified is the electrical resistivity. When the pulses are used of which the polarity is opposite to that of pulses introduced at the initial stage of modification, the property of the material can be inverted at least partially.
Some examples of the cross point memory employing a perovskite material are disclosed in JP-A 2003-68984, JP-A 2003-68983 and JP-A 2003-197877.
The construction and the method for manufacturing such a cross point memory employing a perovskite material will now be explained referring to FIGS. 2 and 6. FIG. 2 illustrates a plan layout view of memory cells in a conventional cross point memory. FIGS. 6(a), 6(b), 6(c), 6(d), 6(e), 6(f), and 6(g) are cross sectional views taken along the line A-A and the line B-B′ of FIG. 2 showing steps of a procedure of manufacturing the conventional memory cells.
The procedure starts with, as shown in FIG. 6(a), depositing a BPSG layer 5 of 1500 nm thick on a silicon semiconductor substrate 4 accompanied with a memory circuit and polishing the same to a thickness of 1000 nm by a CMP (Chemical Mechanical Polishing) process to have a planar surface. Then, a contact plug 6 is provided for connecting between the silicon semiconductor substrate 4 and the lower electrodes 1. In succession, a sputtering process is conducted for depositing on the BPSG layer 5 a 50 nm thickness of TiN layer 7 which is made of a lower electrode material and turns to the lower electrodes 1 and a 150 nm thickness of Pt layer 8 on the TiN layer 7.
This is followed by a photolithography process of providing a stripe, L/S (line and space) pattern of masking resist (not shown) for configuring the lower electrodes and dry etching both the TiN layer 7 and the Pt layer 8 to build the lower electrodes 1 after removal of the resist, as shown in FIG. 6(b). Then, an SiO2 layer 19 is deposited to a thickness of 500 nm by a CVD (Chemical Vapor Deposition) process and flattened by a CMP process to expose the surface of the Pt layer 8.
Then, as shown in FIG. 6(c), an SiO2 layer 20 is deposited to a thickness of 300 nm on the SiO2 layer 19 and the lower electrodes 1 (of the Pt layer 8) by a CVD process. Another lithography process follows for masking with a pattern of resists (not shown) which have an array of openings 3 for forming active layers at the intersections between the lower electrodes 1 and the upper electrodes 2. Then, the SiO2 layer 20 is dry etched at the openings to expose the Pt layer 8 for the active layers.
A sputtering process follows for depositing on the Pt layer 8 and the SiO2 layer 20 a Pr0.7Ca0.3MnO3 (PCMO) layer 21 to a thickness of 200 nm which will turn to the perovskite memory materials as shown in FIG. 6(d). The PCMO layer 21 is then polished by a CMP process to expose the SiO2 layer 20 and then a Pt layer 22 is deposited to a thickness of 100 nm by a sputtering process which will turn to the upper electrodes 2.
This is followed by a photolithography process for providing a corresponding stripe, L/S (line and space) pattern of resist 23 to the upper electrodes 2 at the lower electrodes 1 as shown FIG. 6(e). With the resist 23 used as a mask, the Pt layer 22 is etched by a dry etching process to configure the upper electrodes 2 (of the Pt layer 22) as shown in FIG. 6(f).
Further, an SiO2 layer 14 is deposited to a thickness of 1200 nm on the Pt layer 22 by a CVD process and polished to a thickness of 800 nm by a CMP process to flatten the surface. Then, a pattern of Al wiring 15 is provided for connecting between the Pt layer 22 of the upper electrodes 2 and the silicon semiconductor substrate 4, as shown in FIG. 6(g).
However, each of the conventional methods disclosed in the publications requires a dedicated lithography step of providing a perovskite material at the intersection of the cross point structure. In total, three lithography steps are needed as the dedicated step is added with the two essential steps for patterning the lower electrodes and the upper electrodes. Also, the conventional cross point memory has each intersection between the upper electrode and the lower electrode determined as a memory cell. This area is crucial for determining the level of data density.
In every conventional method, there is needed a margin for positioning the openings 3 over the memory material at the intersections between the lower electrodes 1 and the upper electrodes 2, as shown in FIG. 2. Accordingly, the width of each of the lower electrodes 1 and the upper electrodes 2 will be greater than the minimum of the line width and the interval to be patterned by an applicable process or the minimum of the feasible size in the process. When the minimum is a unit pitch of F, the margin is needed 0.5 F at each side of the width of each of the lower electrodes 1 and the upper electrodes 2 and calculates a total of 2F. The area at the cross point is hence expressed by 3 F by 3 F along both the directions of the lower electrode 1 and the upper electrode 2 respectively. More particularly, the cell area in the semiconductor memory is sized by 3 F×3 F=9 F2 as denoted by the real line in FIG. 2 and will hardly be reduced.